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| ST1305B Memory Card IC 192 bit High Endurance EEPROM With Secure Logic Access Control DATA BRIEFING s s Single Supply Voltage (5 V) Memory Divided Into: - 16 bits of Circuit Identification - 48 bits of Card Identification - 48 bits of Count Data - 16 bits of Certificate - 24 bits of Transport Code - 64 bits of Issuer Data 1 1 1 1 s s Counting Capability up to 262,144 Circuit Protected by Transport Code for Delivery from ST to the Customer 5 External Contacts Only (ISO 7816 Compatible) Answer to Reset (Fully Compatible with ISO 7816-3) E.S.D. Protection Greater Than 4000 V Power-On and Low VCC Reset 1 Million Erase/Write Cycles (minimum) 10 Year Data Retention (minimum) 5 ms Programming Time (typical) Micromodule (D10) Micromodule (D15) s s s s s s s Wafer DESCRIPTION The ST1305B is a 192-bit EEPROM device with associated security logic to control memory access. The circuit includes counting capabilities and thus is very well adapted to prepaid card applications. The ST1305B is protected by hard-wired security logic and special fuses. The memory is arranged as a matrix of 24x8 cells, accessed in a serial bit- Figure 1. Logic Diagram VCC RST ST1305B I/O Table 1. Signal Names CLK RST I/O VCC GND Clock Reset Serial Data Input/Output Supply Voltage Ground CLK GND DS05B01 September 1998 Complete data available on Data-on-Disc CD-ROM or at www.st.com 1/2 ST1305B wise fashion for reading and programming, and in a byte-wise fashion for internal erasing. The device recognises three commands issued via the RST and CLK pins (as described in the full data sheet): - RESET: to reset the internal address register to 00d - READ: to increment the internal address register, and read the data bit at that address - PROG: to program the bit at the current address. Figure 2. Memory Map In USER Configuration 000d 016d Card Identification 48 bits EEPROM Cells Matrix Circuit Identification 16 bits READ ONLY The device offers two distinct configurations: - ISSUER: for the card manufacturer, allowing special data to be written to the chip, during initialisation - USER: for the end user of the card, restricting access to the chip. Before delivery, from ST to the card issuer, the device is placed in the ISSUER configuration. This operation is performed by blowing the "test fuse". 064d Counters / Transport Code 48 bits READ, WRITE, ERASE Certificate 128d Issuer Defined Area 192d Unused 260d 64 bits READ ONLY 16 bits 112d Fuses DS05B07 Table 2. Ordering Information Scheme Example: ST1305B W4 / XX YY Delivery Form D10 D15 W4 Micromodule on Super 35 mm reel Micromodule on Super 35 mm reel Wafer (180 m thickness) Transport Code Given by ST Customer Code Given by the Issuer 2/2 |
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